Embodiments of the present invention relate generally to a semiconductor manufacturing process. More particularly, embodiments of the present invention provide a method to realize stress memorization techniques (SMT) for a high-k metal-gate process to improve transistor performance.
In advanced semiconductor manufacturing processes, stress memorization technique (SMT) is a method often used to improve the performance of N-type field effect transistor (NFET). In conventional SMT techniques, re-crystallization of the polysilicon gate is used to improve the performance of the NFET. When source/drain region ion implantation is performed, inactive dopants are injected into source/drain regions, and the polysilicon gate becomes amorphous. A stress memory material is formed covering the polysilicon gate. After annealing, source/drain regions are activated and, at the same time, the polysilicon gate is re-crystallized. During the re-crystallization process, due to the resistance of the stress memory material layer, the volume expansion of the polysilicon gate electrode is suppressed. As a result, a tensile stress is transferred to the channel region of the semiconductor substrate to improve the carrier mobility.
In conventional SMT techniques, after the stress transfer process, the stress memory material is removed. Then, self-aligned silicide is formed on the source/drain regions. At this point, a masking step is often carried out to form a mask to prevent silicide formation on top of the dummy polysilicon gate, which needs to be removed in a subsequent step. The sidewall spacers on both sides of the polysilicon gate electrode are removed. A contact etch stop layer (CESL) and an interlayer dielectric layer are formed over the gate structure, and chemical mechanical polishing is performed to expose the top of the polysilicon gate. After the polysilicon gate electrode is removed, a high-k gate dielectric layer and a metal gate are formed. A second interlayer dielectric layer is formed over the metal gate and the first interlayer dielectric layer. Next, contact plugs are formed to contact the metal gate and the silicide regions on the source/drain regions.